This application is related to Japanese application No. 2001-019950 filed on Jan. 29, 2001, whose priority is claimed under 35 USC xc2xa7119, the disclosure of which is incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a fabrication process therefor. More particularly, the invention relates to a semiconductor integrated circuit which has a plurality of bump electrodes having a uniform height, and to a fabrication process therefor.
2. Description of the Related Art
In the fields of cellular phones and mobile information terminals in the electronic information industry, attempts have recently been made to increase the integration density of semiconductor devices. For a higher integration density, it is necessary to stably establish electrical and physical connections between minute electrode pads on a semiconductor device and interconnections on a substrate mounted with the semiconductor device.
One exemplary method for the establishment of the connections is to form gold bumps on electrode pads of the semiconductor device. Plating methods are generally employed for the formation of the gold bumps on the semiconductor device. The plating methods are broadly classified into two categories: an electroless plating method and an electrolytic plating method.
In the electroless plating method, a metal of a metal base to be plated is chemically replaced with a metal contained in a plating liquid. Therefore, the electroless plating method is advantageous in that equipment such as a plating power source is not required. However, possible combinations of the metal base and the plating liquid are limited, and a plating rate is relatively low. Therefore, the electroless plating method is not suitable for formation of a metal film having a thickness of ten-odd micrometers to several tens of micrometers as required for the formation of the bumps on the semiconductor device.
In the electrolytic plating method, on the other hand, the plating is electrochemically achieved by passing an electric current through a metal base to be plated and a plating liquid. Therefore, the electrolytic plating method can be applied to a combination of the metal base and the plating liquid to which the aforesaid electroless plating method cannot be applied. In the electrolytic plating method, the plating electric current increases the plating rate as compared with the electroless plating method, and a metal film having a thickness of several tens of micrometers can easily be formed. Therefore, the electrolytic plating method is suitable for the formation of the bumps on the semiconductor integrated circuit.
Next, a bump formation process employing the electrolytic plating method will briefly be described.
A metal base film is first formed on an insulating film provided on a semiconductor substrate (herein referred to as xe2x80x9cwaferxe2x80x9d). Then, a photoresist film is formed on the metal base film, and openings are formed in the photo resist film by a photo lithography technique to expose predetermined portions of the metal base film, i.e., in bump electrode formation areas. Thereafter, a plating electric current is supplied to the metal base film, whereby a metal is deposited on the exposed portions of the metal base film for formation of bump electrodes. There are three conventionally known methods for the supply of the plating electric current.
In a first conventional method, an opening for connection of a plating electrode (herein referred to as xe2x80x9ccathode electrodexe2x80x9d) is formed in the photoresist film in a peripheral area of the wafer when the photoresist film is formed on the metal base film, and then the cathode electrode is connected to the metal base film through the opening. Alternatively, the photoresist film is removed by piercing the photo resist film with the cathode electrode for the connection of the cathode electrode to the metal base film.
More specifically, electrode pads 23 are provided on an insulating film 22 on a wafer 21, and the wafer is covered with a protective film 24 which has openings on the electrode pads 23 in bump electrode formation areas A as shown in FIG. 5. A metal base film 25 is formed over the resulting wafer, and a photoresist film 26 is formed on the metal base film 25. Further, openings are formed in the photoresist film 26 in the bump electrode formation areas A.
The photoresist film 26 is pierced with a cathode electrode 28 for electrical connection of the cathode electrode 28 to the metal base film 25 (though not shown, an opening may be formed in the photoresist film 26 for connection of the cathode electrode to the metal base film).
In turn, the resulting wafer 21 is set in a plating device 101 as shown in FIG. 6. The wafer 21 is supported by the cathode electrode 28 with a bump electrode formation surface thereof facing downward to be opposed to an anode electrode 10.
In the plating device 101, a plating liquid 9 is fountained from an inner lower side of the device toward the bump formation surface of the wafer 21, and discharged from the periphery of the wafer 21 to the outside.
In this state, a voltage is applied between the anode electrode 10 and the cathode electrode 28 connected to the metal base film 25 on the wafer 21, whereby a plating electric current is supplied to the metal base film 25 for formation of bump electrodes 27 (see FIG. 5).
In a second conventional method, a cathode electrode is connected to a portion of the metal base film on a side surface of the wafer (see, for example, Japanese Unexamined Patent Publication No. 1-110751 (1989)) in view of the fact that the metal base film is formed not only on the bump electrode formation surface but also on the side surfaces of the wafer.
More specifically, a metal base film 35 is formed on a bump electrode formation surface and side surfaces of a wafer 31, and a cathode electrode 38 is electrically connected to a portion of the metal base film on the side surface of the wafer as shown in FIG. 7. Thereafter, the resulting wafer is subjected to the plating process in substantially the same manner as in the first method in the aforesaid plating device 101 (See FIG. 6).
In a third conventional method, a metal film electrically connected to the metal base film is formed on a back surface of the wafer, and a cathode electrode is connected to the metal film on the back surface of the wafer (see, for example, Japanese Unexamined Patent Publication No. 3-54829 (1991)).
More specifically, a metal base film 45 is formed as covering a bump electrode formation surface and side surfaces of a wafer 41, and a metal film 46 is formed on a back surface of the wafer 41 so as to be electrically connected to the metal base film on the side surface of the wafer. A cathode electrode 48 is electrically connected to the metal film 46. Thereafter, the resulting wafer is subjected to the plating process in substantially the same manner as in the first method in the aforesaid plating device 101 (see FIG. 6).
In the first conventional method, the plating liquid penetrates through the opening provided for the cathode electrode connection during the plating process in the electrolytic plating device, so that the plating electric current is unevenly supplied to an area other than the bump electrode formation areas. Therefore, a metallization layer is uselessly formed in the unintended area by the plating, and the resulting bump electrodes are nonuniform in height.
Where the photoresist film is pierced with the cathode electrode to be removed, it is difficult to control the removal of the photoresist film. If the removal of the photoresist film is excessive, the aforesaid problem occurs. If the removal of the photoresist film is insufficient, an electrical connection cannot sufficiently be established between the cathode electrode and the metal base film, resulting in uneven supply of the plating electric current. Therefore, the resulting bump electrodes are nonuniform in height.
In the second conventional method, the metal base film is exposed on the side surfaces of the wafer, so that the plating liquid is easily brought into contact with the side surfaces of the wafer. Therefore, a metallization layer is uselessly formed on the side surfaces of the wafer, and the resulting bump electrodes are nonuniform in height.
In the third conventional method, the cathode electrode is connected to the metal film formed on the back surface of the wafer, so that the plating electric current is supplied to the bump electrode formation areas via the periphery of the wafer. Since distances between the periphery of the wafer and each bump formation area in the semiconductor integrated circuit formed on the wafer are different, plating potentials occurring in the bump formation areas are different.
Further, the metal base film has variations in thickness due to steps on the surface of the semiconductor integrated circuit on the wafer, so that the metal base film has variations in resistance depending on the position on the wafer. Due to these problems, the amperage of the plating electric current supplied to the metal base film varies depending on the position on the wafer, so that the resulting bump electrodes are nonuniform in height.
In the first to third conventional methods, a common approach is to supply the plating electric current via the periphery of the wafer, so that the amperage of the supplied plating electric current varies depending on the position on the wafer. Therefore, the first to third methods fail to form bump electrodes having a uniform height on the wafer.
Where bump electrodes having a height of about 20xcexcm are to be formed on 6-inch wafer, for example, a maximum height variation of the bump electrodes is about 6xcexcm in the first conventional method, about 5xcexcm in the second method, and about 4xcexcm in the third method.
In view of the foregoing, the present invention is directed to a semiconductor integrated circuit having bump electrodes of a uniform height and a fabrication process in which a plating electric current is evenly supplied over a wafer in an electrolytic plating process for formation of the bump electrodes.
In accordance with the present invention, there is provided a semiconductor integrated circuit which comprises a semiconductor substrate (wafer) having a plurality of bump electrode formation areas and a bump electrode non-formation area respectively defined on a front surface thereof; a first electrode pad formed in the bump electrode non-formation area; a second electrode pad formed in each bump electrode formation area; and a bump electrode formed on each second electrode pad; wherein the first electrode pad is used for supplying a plating electric current to the second electrode pads through the semiconductor substrate in formation of the bump electrodes by electrolytic plating.